1. Field of the Disclosure
The present disclosure relates, generally, to an electronic apparatus including a reconfigurable very long instruction word (VLIW) processor that is configured to process a VLIW instruction.
2. Description of the Related Art
As instruction per cycle (IPC) of reduced instruction set computers (RISC) becomes more and more limited, studies have been started to increase performance of a processor by increasing instruction level parrallism (ILP), and as a result, processors such as a VLIW processor, a superscalar processor, an explicitly parallel instruction computing (EPIC) processor, and the like have been developed. In order to increase the ILP, a scheduling technology of determining the order and point of time of instructions is required, where a compiler plays an important role. In particular, with respect to the VLIW, various scheduling techniques in which the compiler maximizes the ILP based on data dependency, register pressure analysis, and the like have been studied.
With respect to the VLIW, the compiler analyzes the data dependency to designate an order of instructions, an execution function unit, and an issue point of time. Conversely, with respect to the superscalar processor, the processor analyzes a relationship between created instructions to designate the execution function unit and the issue point of time.
With respect to the superscalar processor, a point of time at which an operation of one instruction is completed is predefined, and an operation of a next instruction starts after a point of time at which an operation of a previous instruction is completed. Since a multiplying (mul) instruction, a division (div) instruction, and the like have a very long latency, continuous no operational (nop) instructions or stall instructions are added to wait a result of the operation.
However, in applications that process a large amount of information, e.g., signal processing, a computer vision, a big data analysis, and the like, only a very small portion of an input data may have a valid value, and a significant portion of the input data may have an invalid value.